In a conventional master-slave memory circuit having a bus system, bus masters access the memory through bus arbitration schemes that must guarantee low latency or meet bandwidth requirements. Related Art FIG. 1 shows an example 100 of such a system, having master devices 102-1, 102-2 . . . 102-N (collectively 102) connected to bus masters interfacing to the bus interconnect 104. Various traffic patterns along available paths 106 may be determined by bus arbiters such as 108. One or more memories 112 couple to respective memory controllers 110, which couple to slave devices interfacing to the bus 104. In these conventional designs, efficiency of accesses to the memories 112 heavily depends on the traffic patterns determined by the bus arbiters 108, as well as address request patterns, and the design of the memory controller and memory itself Further, in conventional arrangements, memories 112 may not be fully utilized due to temporal load unbalance. During times of heavy bus utilization, for example, the bus 104 may form a process flow bottleneck that delays memory access for some access requests by the bus masters. Further, during times of light bus utilization, the memories 112 may be under-utilized, and result in memory access capacity being wasted.
FIG. 2 shows a computer simulation 200 of memory accesses to a conventional master-slave, for example the memory formed by the FIG. 1 memory 112 and its memory controller 110 in the FIG. 1 depicted bus system 100. The computer simulation 200 is over a time interval TT along a time axis 202, marked according to contiguous equally spaced sampling intervals. At each of the sampling intervals is a vertical bar, having a height representing the quantity of memory requests carried out by the above-described slave memory over that sampling interval. It will be understood that the total of the accesses over the TT interval accomplishes, in terms of an amount of data transferred, a given benchmark task. For convenience in referring to FIG. 2, periods of predominantly read requests are filled in black and periods of predominantly write requests are marked by cross-hatching.
The temporal load imbalance shown by the FIG. 2 simulation is significant. Over time intervals LT1, LT2 and LT3, the average number of read accesses per subinterval is low. Contrasting sharply, packed into the much shorter time periods HT1, HT2, and HT3 are write accesses arriving at the slave memory at a rate multiple times the read access density over LT1, LT2 and LT3. Stated differently, for approximately 90% of the TT interval used to perform the given benchmark task, the slave memory is handling only ⅕ the access density that it may be capable of handling. Further, if the access density during the HT1, HT2, and HT3 high load intervals is high enough to cause degradation in system performance then, for the small percentage of the time the memory is not severely under-utilized it is, instead, over loaded.